A current common requirement for an electronic circuit and particularly for electronic circuits manufactured as integrated circuits in semiconductor processes is an array of memory storage elements. These elements may be provided as non-volatile memory (NVM) cells. In traditional NVM structures, FLASH memory may be used. However the use of FLASH memory requires semiconductor processing steps in addition to the advanced semiconductor processing used for logic circuitry, for example. The FLASH cells require expensive process steps. More recently, logic compatible NVM cells have been developed. Some of these logic compatible memory cells use a floating gate which is formed using the gate electrode materials and gate oxides of the logic processes. As the process nodes for semiconductor processes continue to scale to smaller feature sizes, the gate oxide thicknesses (Tox) also are reduced to a point where reliable floating gate cells may not be reliably produced. Leakage of current from the stored trapped charges may result in inoperable or unreliable storage cells; that is, the floating gate cells may experience errors due to leakage.
NVM cells using sidewall storage are in use. In these cells a charge trapping layer is provided in the sidewall dielectrics of a cell form that includes, for example, a MOS transistor such as PMOS or NMOS transistor. By using channel hot electrons (CHE) to “program” the cells, electrons may be trapped in a charge trapping dielectric on the sidewall. However, when a single sidewall storage area is used to store a bit of information, in a “one cell per bit” arrangement, reliable operation is difficult to obtain. Variations in the programmed and unprogrammed currents for the cells have been observed. These variations make reliable operation difficult.
In another known approach, these reliability problems are addressed by using two cells to store one bit of information, in a “two cells per bit” structure. These may be referred to as “2T” cells. In this approach, one cell stores the desired data, and the other cell stores the desired data in a complementary form, that is “bit” and “bit bar”. By using two separate bit lines to read data from both of these cells during a read cycle, a self-referenced data value may be obtained by simply comparing the currents (or corresponding voltages) on the bit and bit bar bit lines. Since one of the two cells will be programmed and the other will be unprogrammed, the programmed and unprogrammed states representing a stored logic “0” and a stored logic “1”, the two currents will differ and may be easily compared, and a very rapid read may be obtained.
However the use of two cells per bit effectively doubles the cell array size needed to store data. These cells are considered “2T” cells and require about twice the area per bit when compared to one cell per bit or “1T” arrangements (one transistor per bit). Improvements are needed in the reliability and the density of non-volatile memory storage cells that are logic process compatible; that is, non-volatile storage cells are needed that may be produced on an integrated circuit embedded with logic circuitry in an advanced semiconductor process, without the need for additional steps or expensive process steps.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.